Know all about Instruction Pipeline in Computer Architecture



A program consists of multiple instructions which are to be performed in sequential steps.

An instruction pipeline reads consecutive instructions from memory while previous instructions are being executed in other segments. This technique is used to increase the throughput of computer systems. This causes the instructions to fetch and execute overlap and perform simultaneous operations. The instruction pipeline execution will be like queue execution (i.e. FIFO). Therefore, when instruction first comes will be placed in a queue and will be executed in the system. Finally, the result will be passed onto the next instruction in the queue.

Order of execution of Instruction in pipeline

1.      Fetch the instructions from memory

2.      Decode the instructions

3.      calculate the effective address

4.      Fetch the operands from memory

5.      Execute the instructions

6.     Store the result in the proper place

Four-Segment Instruction Pipeline

four-segment instruction pipeline combines two or more different segments and makes it a single one. For instance, the decoding of the instruction can be combined with the calculation of the effective address into one segment.

Four-segment CPU pipeline

Segment 1:

FI=>The instructions fetch segment can be implemented using a first in first out (FIFO)buffer.

Segment 2:

DA=>The instructions fetched from memory are decoded in the segment, and eventually, the effective address is calculated in a specific arithmetic circuit.

Segment 3:

FO=>An operand from memory is fetched in the third segment

Segment 4:

EX=>The instruction is finally executed in the instructions.

Four Segment CPU Pipeline


In the flowchart, if the branch instruction takes place then a pipeline stall will take place in which the next instruction execution will be cleaned up. The pipeline will be made empty. Then program counter will be updated with the target address from where the next target instruction has to be read and executed and then the process will restart. And if an interrupt has occurred the program will get postponed. The program control will go to interrupt handling routine, to handle the interrupt for what it has been caused. Again empty pipe will take place after updating the program counter. The process will restart with new target instruction from the address. So in this way instruction pipeline will get executed. 

Timing of Instruction Pipeline

The instruction is fetched for the first instruction. In the second cycle, it will go to the instruction decode, then the second instruction will come to the instruction fetch. In the third cycle, the first instructions will go to operand fetch and instruction will come to instruction decode and the third instruction will be coming for instruction fetch.


As we know instructions in pipeline architecture are executed phase-wise. Say in the third instruction the instruction has a category of branching or jumping of conditional or unconditional. Then linear or sequential execution of instructions gets hampered.

As a result, the next instruction which third instruction in the program will not execute because due to the presence of jump or goto instruction program control is supposed to get transferred toward a different memory space to the target memory location. But that will be remained unknown until a branch instruction is decoded. So as a result of that this instruction execution will be blocked and in these phases, these particular cycles will remain unutilized for the fourth instruction.

So after the completion of the third instruction when it will be sure that instruction control is going to that particular address then from the target address the next instruction will be fetched, and the process will be resumed. This is known as pipeline stall, so the pipeline has been halted as a result of that we see so many phases are there and so many time cycles are there for which this pipeline remains utilized and remains halted. The pipeline efficiency remains decreased, the pipeline throughput will also get decrease and causes deterioration of the pipeline.

CSIT Computer Architecture Instruction pipeline Notes

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