What is a Common Bus System

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A pair of signal lines that facilitate the transfer of multi-bit data from one system to another is known as a bus. The common bus is required in the computer for communication with registers and memory to decrease the hardware complexity.

The basic computer has eight registers, a memory unit and control unit. The path is required to transfer data, address and control signal. If there is a wire for every operation and every address of memory location, then it will be excessive. So common bus system is implemented through use of MUX and other circuit for proper implementation of wire.

Types of Registers

Instructions Registers(IR)Hold instruction code of instruction currently executing
Address Registers(AR)All memory references are initiated by loading the memory address in AR
Temporary Registers(TR)Extra registers used to store data and address
Input Registers(IR)Hold the data from input devices
Output Registers(OR)Hold the data to send to output devices
Program Counter(PC)Holds the address of next instruction to be executed
Accumulator(AC)Store results produced by system
Data Registers(DR)Temporarily store data being transmitted to or from peripheral devices

Common Bus System

Common bus architecture figure

Three control lines S2, S1, S0 control which registers the bus selects as its input. Either one of the registers will have its load signal activated, or the memory will have its read signal activated.

  • Six registers and a memory are connected to a bus.
  • The input register INPR and OUTR HAS 8 bit each.
  • The seven registers, memory, INPR, and OUTR are driven by a single phase clock pulse.
  • The particular register whose load (LD) input is enabled receives the data from the bus during the next clock pulse.
  • Five registers have three control inputs: load(LD), Increment(INR), and clear(CLR). Two registers IR and OUTR have only LD inputs.
  • The result is transferred to AC and end carry is transferred to flip-flop E.

Read about: Instruction Pipeline, Arithmetic Pipeline


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